1. Field of the Invention
This invention relates to interconnection circuitry and, more particularly, to improved apparatus for handling data within a computer system in a manner that a plurality of data sources can transfer a very large amount of information to a plurality of destinations concurrently.
2. History of the Prior Art
The typical computer system utilizes a busing arrangement as the interconnection to transfer information from one component of the system to another. Such a busing arrangement often includes an address bus and a data bus. Each of these buses is made up of a number of conductors (for example, thirty-two) which physically connect to each of the major system components. For example, a central processor, main memory, a frame buffer, and an input/output controller may all connect to the system bus. When information is transferred between system components (for example, when information is written from a source component to a destination component), the source component signals that it has information ready for transfer. During the time that any particular component is utilizing the buses, they are unavailable for use by any other one of the components since all of the conductors of each bus available to carry either address or data information are occupied. Consequently, information may be written by only one source component or read by only one destination component at one time (although more than one destination component may receive information if more than one destination component can respond to the same address) since there is room for information from only one source component on the lines of the data or address buses. For this reason, some form of arbitration circuitry reviews all of the source components with information available for transfer and decides which component should be allowed to transfer information. In a write operation, the source component selected to transfer its information places an address indicating the destination on the address bus and the data to be transferred on the data bus. The destination component recognizes an address within its range of addresses and accepts the information available on the data bus. In the case of a read operation, the component desiring the information places an address indicating the source of the data on the address bus and waits for the data to be transferred to it on the data bus.
In the past, busing arrangements have sufficed for transferring information in the typical personal computer or work station. The typical manner of increasing the proficiency of the bus is to provide a wider data path and increase the clock speed. However, the requirements for pathways to handle more and more information faster have increased to the point that various functions cannot be performed economically by the typical busing arrangement. Functions such as the presentation of animated graphics and television require the transfer of so much information that the entire busing arrangement of present day systems must be devoted to their use. When it is desired to incorporate a number of these functions into the same computer system and to run a number of these operations simultaneously, a typical busing arrangement capable of handling the load becomes very difficult to design and very expensive to implement. For example, to operate at frequencies over approximately 25 megahertz, it is necessary to control the parasitic capacitance and the impedance of all devices connected to the bus very tightly and to substantially increase the size of the drivers used. This drastically increases the cost of designing devices and the complexity of the devices designed for use with the system. Moreover, it essentially eliminates the ability of the system to operate with inexpensive devices designed for earlier systems. Although the desired performance can be attained, increasing the size of the bus and the frequency of operation does not present a desirable cost/complexity tradeoff.